Dissemination of IT for the Promotion of Materials Science (DoITPoMS)

DoITPoMS Teaching & Learning Packages Electromigration Problems associated with the increase in resistance

# Problems associated with the increase in resistance

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The equations below show the interlinking relationships between resistance, capacitance, and resistor-capacitor (RC) delay with line width, L:

$$\displaylines{ {\rm{Resistance, }}R' = {{L\rho } \over A} = {{L\rho } \over {W{t_{metal}}}} \cr {\rm{Capacitance, }}C = \varepsilon {\varepsilon _0}{A \over d} = \varepsilon {\varepsilon _0}{{{t_{metal}}L} \over D} \cr {\rm{RC time delay }} = {\rm{ (}}R \times C) \propto {\rm{ }}\rho \varepsilon {\varepsilon _0}{{{L^2}} \over {WD}} \cr}$$

where: L = length of metallization line (m), tmetal = thickness of line (m),A = cross‑sectional area (m2), d = distance between conductors (m), W = width of metallization line (m); εo = permittivity of free space (8.85×10-12 F m-1); and ε = dielectric constant.

In the operation of an IC, it is therefore important that resistances of interconnects, vias and contacts remain within the range specified in the circuit design. Due to the effect it has on the RC time delay (see definition below), a change of resistance of 10% is enough to cause problems. In electromigration testing, a 10% change in resistance is often taken to represent “failure” (note how much less extreme an event this is compared to the formation of an open or short circuit).

The RC time delay is the major factor limiting device speed – also known as clock speed – the speed in which a microprocessor executes instructions. Therefore, the associated increase in resistance due to electromigration causes a longer RC time delay, resulting in slower clock speed, thus fewer instructions can be executed by the CPU per second.